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82562EP 10/100 Mbps Platform LAN Connect (PLC)
Networking Silicon
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Datasheet
Product Features

IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction Alert on LAN functionality

Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in "unplugged mode" (less than 50 mW) Automatic detection of "unplugged mode" 3.3 V device Lead-free1 64-pin Plastic Ball Grid Array Package for both leaded and lead-free designs. (Devices that are lead-free are marked with a circled "e1" and have the product code prefix: PCxxxxxx).
1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.
Revision 2.0 September 2005
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Revision History
Revision 1.0 1.4 1.5 1.6 2.0 Revision Date August 2000 May 2001 October 2001 December 2003 September 2005 Initial release (Intel Secret). Finialized signal descriptions and pinouts. Changed document status to Intel Confidential - Controlled Access. Removed confidential status. Updated or new revision information includes: * * * * * Lead-free information. Product codes. Bias reference resistor values (RBIAS 10 and RBIAS 100). Crystal input/output clock values. Signal termination section. Description
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562EP PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2005, Intel Corporation * Other brands and names are the property of their respective owners.
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Contents
1.0 1.1 1.2 1.3 2.0 2.1 2.2 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4.0 4.1 4.1.1 4.1.2 5.0 5.1 5.2 6.0 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 7.0 7.1 7.1.1 Introduction......................................................................................................................... 1 Overview ...................................................................................................................... 1 References................................................................................................................... 1 Product Codes ............................................................................................................. 1 82562EP Architectural Overview........................................................................................ 3 LAN Connect Interface.................................................................................................3 Hardware Configuration ............................................................................................... 4 82562EP Signal Descriptions............................................................................................. 5 Signal Type Definitions ............................................................................................... 5 Twisted Pair Ethernet (TPE) Pins ............................................................................... 5 External Bias Pins ....................................................................................................... 5 Clock Pins ................................................................................................................... 6 Platform LAN Connect Interface Pins ......................................................................... 6 LED Pins .....................................................................................................................7 Miscellaneous Control Pins ......................................................................................... 7 Power and Ground Connections ................................................................................. 8 Signal Terminations............................................................................................................ 9 Terminating Resistors .................................................................................................. 9 Termination Plane................................................................................................10 Termination Plane Capacitance...........................................................................10 82562EP Test Port Functionality......................................................................................11 Asynchronous Test Mode ..........................................................................................11 Test Function Description ..........................................................................................11 Electrical and Timing Specifications.................................................................................13 Absolute Maximum Ratings .......................................................................................13 DC Characteristics ....................................................................................................13 X1 Clock DC Specifications ................................................................................13 LAN Connect Interface DC Specifications ..........................................................14 LED DC Specifications .......................................................................................14 10BASE-T Voltage and Current DC Specifications ............................................14 100BASE-TX Voltage and Current DC Specifications ........................................15 Package and Pinout Information ......................................................................................17 Package Information ..................................................................................................17 82562EP Pin Assignments .................................................................................19
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Figures
1 2 3 4 5 6 82562EP PLC Block Diagram ............................................................................... 3 82562EP PLC 10/100 Mbps Ethernet Solution ..................................................... 3 Termination Resistors Placement (Integrated Magnetics Solution) ...................... 9 Dimension Diagram for the 82562EP 64-pin PBGA (1 of 2) ............................... 17 Dimension Diagram for the 82562EP 64-pin PBGA (2 of 2) ............................... 18 82562EP Pinout Diagram.................................................................................... 20
Tables
1 2 3 4 5 6 7 8 9 10 11 82562EP Hardware Configuration ........................................................................ 4 XOR Tree Chain Order ....................................................................................... 11 General DC Specifications .................................................................................. 13 X1 Clock DC Specifications ................................................................................ 13 LAN Connect Interface DC Specifications .......................................................... 14 LED DC Specifications........................................................................................ 14 10BASE-T Transmitter ........................................................................................ 14 10BASE-T Receiver ............................................................................................ 15 100BASE-TX Transmitter.................................................................................... 15 100BASE-TX Receiver........................................................................................ 15 82562EP Pin Assignments.................................................................................. 19
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1.0
1.1
Introduction
Overview
The Intel(R) 82562EP is a highly-integrated Platform LAN Connect (PLC) device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562EP complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562EP also includes a PHY interface compliant to the current PLC interface.
1.2
References
* IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers.
* LAN Connect Interface Specification. Intel Corporation. * I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
Programming information can be obtained through your local Intel representatives.
1.3
Product Codes
The product ordering code for a lead-free device is: PC82562EP. The product ordering code for a leaded device is: RC82562EP.
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2.0
82562EP Architectural Overview
The 82562EP is a highly integrated Platform LAN Connect device that combines 10BASE-T and 100BASE-TX physical layer interfaces. The 82562EP supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1 shows a block diagram of the 82562EP architecture.
Digital Equalizer Adaptation Equalizer & BLW correction MDI/MDI-X CRS/Link 10 Detection Transmit DAC 10/100 AutoNegotiation Bias & BandGap Voltage Circuit Clock Generator Control Registers Digital Clock Recovery (100) Digital Clock Recovery (10) 100Base-TX PCS
LAN_RSTSYNC
Port LED Drivers
LILED# ACTLED# SPDLED#
RDN/RDP
10Base-T PCS LAN Connect Interface
3 3
LAN_TXD[2:0] LAN_RXD[2:0] LAN_CLK
TDN/TDP
X1
Crystal 25 MHz
X2
Figure 1. 82562EP PLC Block Diagram
2.1
LAN Connect Interface
The 82562EP supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562EP. The LCI uses an 8-pin interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In addition, its signaling protocol provides greater functionality, such as dynamic power reduction, from a PLC in comparison to a standard MII PHY. Figure 2 shows how the 82562EP can be used in a 10/100 Mbps ICHx design.
I/O ControlHub 4 I/O Control Hub LAN Controller (ICH4) LAN
Controller
82562EZ (Platform LAN 82562EP Connect PLC Device)
Transmit Differential Pair (TDP/TDN) Receive Differential Pair (RDP/RDN)
Magnetics System Bus Interface
Figure 2. 82562EP PLC 10/100 Mbps Ethernet Solution
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2.2
Hardware Configuration
Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test Execute (ISOL_TEX), define the general operation of the device. Table 1 shows the pin settings for the different modes of operation.
Table 1.
82562EP Hardware Configuration
Mode of Operation Normal Operating Mode Isolate Mode (Tri-State and Full Power-Down Mode) XOR Tree TESTEN 0 ISOL_TCK 0 ISOL_TI 0 ISOL_TEX 0 Comments The ISOL_TCK, ISOL_TI, and ISOL_TEX pins can remain floating. The device is in tri-state and power-down mode. The device is in tri-state and power-down mode. The XOR tree is used for board testing and tri-state mode.
0 1 1
1 1 0
1 1 0
1 1 0
NOTE: Combinations not shown in Table 1 are reserved and should not be used.
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3.0
3.1
82562EP Signal Descriptions
Signal Type Definitions
Type I O I/O MLT B DPS APS Name Input Output Input/Output Multi-level analog I/O Bias Digital Power Supply Input pin to the 82562EP. Output pin from the 82562EP. Multiplexed input and output pin to and from the 82562EP. Multi-level analog pin used for input and output. Bias pin used for ground connection through a resistor or an external voltage reference. Digital power or ground pin for the 82562EP. Description
Analog Power Analog power or ground pin for the 82562EP. Supply
3.2
Twisted Pair Ethernet (TPE) Pins
Pin Name TDP TDN Pin Number G3 H3 Type MLT Description Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer.
RDP RDN
H6 G6
MLT
3.3
External Bias Pins
Pin Name RBIAS10 RBIAS100 Pin Number F2 F1 B B Type Description Reference Bias Resistor (10 Mbps). This pin should be connected to a pull-down resistor.a Reference Bias Resistor (100 Mbps). This pin should be connected to a pull-down resistor.a
a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/ low MDI transmit amplitude. See Section 4.0 for more information.
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3.4
Clock Pins
Pin Name X1 Pin Number C2 I Type Description Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better. Otherwise, X1 is driven by an external metaloxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better.
X2
C1
O
3.5
Platform LAN Connect Interface Pins
Pin Name LAN_CLK Pin Number A4 Type O Description LAN Connect Clock. The LAN Connect Clock is driven by the 82562EP on two frequencies depending on operation speed. When the 82562EP is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: * Reset. When this pin is asserted beyond one LAN Connect Clock period, the 82562EP uses this signal as Reset. To ensure the 82562EP is reset, this signal should remain active for at least 500 s. Synchronize. When this pin is activated synchronously for only one LAN Connect Clock period, it is used to synchronize the MAC and PHY on PLC word boundaries.
LAN_RSTSYNC
B3
I
*
LAN_TXD[2:0]
B1 B2 A2
I
LAN Connect Transmit Data. The PLC transmit pins are used to transfer data from the MAC device to the 82562EP. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. These pins should be fully synchronous to LAN_CLK. LAN Connect Receive Data. The PLC receive pins are used to transfer data from the 82562EP to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK.
LAN_RXD[2:0]
A5 A6 B6
O
6
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3.6
LED Pins
Pin Name LILED# Type O Description Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either mode, the LILED# is asserted. Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. The flicker rate depends on the activity load. The individual address LED control bit in the ICH2 EEPROM (Word Ah, bit 4) can select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in Wake on LAN (WOL) mode. 0b = In WOL mode, the ACTLED is activated by the transmission and reception of broadcast and individual address match packets. 1b = In WOL mode, the ACTLED is activated by the transmission and reception of individual address match packets only. This bit is configured by the OEM and is activated by a transmission and reception of individual address match packets. SPDLED# O Speed LED. The LED is active low and the Speed LED signal indicates the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX operation and off in 10BASE-T mode.
ACTLED#
O
3.7
Miscellaneous Control Pins
Pin Name ADV10 I Type Description Advertise 10 Mbps Only. The this signal is asserted high, the 82562EP advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562EP advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. ISOL_TCK I Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal pull-down resistor. ISOL_TI I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal pull-down resistor. ISOL_TEX I Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1). In the manufacturing test mode, it places the command that was entered through the ISOL_TI pin in the instruction register. Note: ISOL_TEX has an internal pull-down resistor. TOUT TESTEN O I Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. Test Enable. The Test Enable pin is used to enable test mode and should be tied to the pull-down resistor for normal operation.
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3.8
Power and Ground Connections
Pin Name VCC VCCA VCCA2 VCCP VCCT VSS Pin Number A1, A8, E7, F7, F8 G1, H1 D2, E2 B4, B5 G4, G5, H4, H5 C3, C6, D3, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6 G2, H2 D1, E1 C4, C5 G8, H8 APS Analog Power. These pins should be isolated from the main power using a resistor-capacitor (RC) filter. A ferrite bead may also be used in place of the resistor. Analog Ground. These pins should not be isolated from the main digital. DPS Digital Ground. These pins should be connected to the main digital ground. Type DPS Description Digital 3.3 V Power. These pins should be connected to the main digital power supply.
VSSA VSSA2 VSSP VCCR
VSSR
G7, H7
APS
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4.0
4.1
Signal Terminations
Terminating Resistors
Two differential pairs are terminated using 54.9 (1% tolerance) resistors, placed near the LAN controller. One resistor connects to the MDI+ (MDI positive) signal trace and another resistor connects to the MDI- (MDI negative) signal trace. Termination resistor values were recently increased from 49.9 to 54.9 to improve return loss. However, on some designs, this change caused the PCB's output amplitude to be slightly above the peak-to-peak center of the IEEE specification. As a result, RBIAS resistor values were increased (RBIAS10 549 to 619 and RBIAS100 619 to 649 ) to reduce the PCB's output amplitude to better meet the IEEE peak-to-peak center specification. For 100Base-TX designs, the IEEE specification allows a -950 mVpk to -1050 mVpk for the negative peak and +950 mVpk to +1050 mVpk for the positive peak. Ideally, a typical PCB output amplitude should be within -975 mVpk to -1025 mVpk for the negative peak and +975 mVpk to +1025 mVpk for the positive peak. For 10Base-T designs, the IEEE specification allows a -2.2 mVpk to -2.8 mVpk for the negative peak and +2.2 mVpk to +2.8 mVpk for the positive peak. Ideally, a typical PCB output amplitude should be within -2.35 mVpk to -2.55 mVpk for the negative peak and +2.35 mVpk to +2.55 mVpk for the positive peak. The RBIAS values previously listed should be considered starting values. Intel recommends that board designers measure each of their PCB's output amplitude and then adjust the RBIAS values as required.
Figure 3. Termination Resistors Placement (Integrated Magnetics Solution)
LAN Connect Interface
82562EP PLC
Magnetics Module
RJ-45
Place Termination Resistors as Close to the 82562EP as Possible
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4.1.1
Termination Plane
Resistors are used to terminate noise from the unused inputs of both the RJ45 connector and the magnetics module to the termination plane. The netname "termplane" is provided as a guide to the termination plane. A termplane is a plane fabricated into the PCB substrate. This plane, which has no DC termination, acts like one-half of a capacitor that provides a path for the coupled noise.
4.1.2
Termination Plane Capacitance
It is recommended that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP and TDN and RDP and RDN) from the unused pairs of the RJ45. Pads may be placed for additional capacitance, which may be required if failure occurs during electrical fast transient testing. Note: This capacitor must be designed to tolerate 2 KV voltage injections to meet International Special Committee on Radio Interference (CISPR) Electrostatic Discharge (ESD) specifications.
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5.0
82562EP Test Port Functionality
The 82562EPG's XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing.
5.1
Asynchronous Test Mode
An asynchronous test mode is supported for system level design use. The modes are selected through the use of the Test Port input pins (TESTEN, ISOL_TCK, ISOL_TI and ISOL_TEX) in static combinations. During normal operation the test pins must be pulled down through a resistor (pulling Test high enables the test mode). All other port inputs may have a pull-down at the designers discretion.
5.2
Test Function Description
The 82562EP TAP mode supports several tests that can be used in board level design. These tests can help verify basic functionality and test the integrity of solder connections on the board. The tests are described in the following sections. The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82562EP to be validated at board test. The XOR Tree was chosen for its speed advantages. Modern Automated Test Equipment (ATE) can perform a complete peripheral scan without support at the board level. This command connects all output signals of the input buffers in the device periphery into an XOR Tree scheme. All output drivers of the output-buffers, except the test output (TOUT) pin, are put into high-Z mode. These pins are driven to affect the tree's output. Any hard strapped pins will prevent the tester from scanning correctly. The XOR Tree test mode is obtained by placing the test pins in the following configuration (refer to Table 2): TESTEN = 1 ISOL_TCK = 0 ISOL_TI = 0 ISOL_TEX = 0. Table 2. XOR Tree Chain Order
Chain Order 1 2 3 4 5 6 7 8 9 10 Chain LAN_TXD2 LAN_TXD1 LAN_TXD0 LAN_RSTSYNC ADV10 LAN_CLK LAN_RXD2 LAN_RXD1 LAN_RXD0 ACTLED#
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Table 2.
XOR Tree Chain Order
Chain Order 11 12 SPDLED# LILED# Chain
XOR Tree Output TOUT
The following pins are not included in the XOR Tree chain: X1, ISOL_TCK, ISOL_TEX, ISOL_TI and TESTEN.
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6.0
6.1
Electrical and Timing Specifications
Absolute Maximum Ratings
Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 135 C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 C to 150 C Supply Voltage with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562EP device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2
Table 3.
DC Characteristics
General DC Specifications
Symbol VCC T P Parameter Supply Voltage Temperature Power Consumption Minimum/Maximum Case Temperature 10/100 Mb/s (transmitter on) Reduced Power Auto-Negotiation Condition Min 3.0 0 300 50 200 Typical 3.3 Max 3.45 85 Units V C mW mW mW Notes
6.2.1
Table 4.
X1 Clock DC Specifications
X1 Clock DC Specifications
Symbol VIL VIH IILIH CI Parameter Input Low Voltage Input High Voltage Input Leakage Currents Input Capacitance 0 < VIN < VCC 2.0 10 8 Condition Min Typical Max 0.8 Units V V A pF 1 Notes
NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only.
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6.2.2
Table 5.
LAN Connect Interface DC Specifications
LAN Connect Interface DC Specifications
Symbol VCCJ VIL VIH IIL VOL VOH CIN Parameter Input/Output Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Input Pin Capacitance 0 < VIN < VCCJ IOUT = 1500 A IOUT = -500 A 0.9VCCJ 8 Condition Min 3.0 -0.5 0.6VCCJ Typical Max 3.45 0.3VCCJ VCCJ + 0.5 10 0.1VCCJ Units V V V A V V pF 1 Notes
NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only.
6.2.3
Table 6.
LED DC Specifications
LED DC Specifications
Symbol VOLLED VOHLED Parameter Output Low Voltage Output High Voltage Condition IOUT = 10 mA IOUT = -10 mA 2.4 Min Typical Max 0.7 Units V V Notes
6.2.4
Table 7.
10BASE-T Voltage and Current DC Specifications
10BASE-T Transmitter
Symbol VOD10 Parameter Condition Min 2.2 Typical Max 2.8 Units V Notes 1
Output Differential RL = 100 Peak Voltage
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN.
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Table 8.
10BASE-T Receiver
Symbol RID10 VIDA10 Parameter Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage DC 5 MHz f 10 MHz 585 5 MHz f 10 MHz 300 mV 3100 mV Condition Min 10 Typical Max Units K Notes 1
VIDR10
VICM10
VCC/2
V
NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN.
6.2.5
Table 9.
100BASE-TX Voltage and Current DC Specifications
100BASE-TX Transmitter
Symbol VOD100 Parameter Condition Min 0.95 Typical 1.0 Max 1.05 Units V Notes 1
Output Differential RL = 100 Peak Voltage
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN.
Table 10. 100BASE-TX Receiver
Symbol RID100 VIDA100 Parameter Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage VCC/2 DC Condition Min 10 Typical Max Units K Notes 1
500
1200
mV
VIDR100
100
mV
VICM100
V
NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN.
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7.0
7.1
Package and Pinout Information
Package Information
The 82562EP is a lead or lead-free 64-pin Plastic Ball Grid Array (PBGA). The package dimensions are shown in Figure 4 and Figure 5. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office.
Figure 4. Dimension Diagram for the 82562EP 64-pin PBGA (1 of 2)
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Figure 5. Dimension Diagram for the 82562EP 64-pin PBGA (2 of 2)
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7.1.1
82562EP Pin Assignments
Table 11. 82562EP Pin Assignments
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 Pin Name Vcc LAN_TXD0 ADV10 LAN_CLK LAN_RXD2 LAN_RXD1 ACTLED# Vcc LAN_TXD2 LAN_TXD1 Pin Number C1 C2 C3 C4 C5 C6 C7 C8 D1 D2 Pin Name X2 X1 Vss Vssp Vssp Vss ISOL_TEX ISOL_TI Vcca2 Vcca2 Vss Vss Vss Vss Tout LILED# Pin Number E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 Pin Name Vssa2 Vssa2 Vss Vss Vss Vss Vcc TESTEN RBIAS100 RBIAS10 Vss Vss Vss Vss Vcc Vcc Pin Number G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Pin Name Vcca Vssa TCP Vcct Vcct RDN Vssr Vccr Vcca Vssa TDN Vcct Vcct RDP Vssr Vccr
LAN_RSTSYNC D3 Vccp Vccp LAN_RXD0 SPDLED# ISOL_TCK D4 D5 D6 D7 D8
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1
2
3
4
5
6
7
8
A
Vcc
LAN_ TXD 0
ADV 10
LAN_ CLK
LAN_ RXD 2
LAN_ RXD 1
ACTLED#
Vcc
B
LAN_ TXD2
LAN_ TXD1
LAN_ RSTSYNC
Vccp
Vccp
LAN_ RXD 0
SPDLED#
ISOL_ TCK
C
X2
X1
Vss
Vssp
Vssp
Vss
ISOL_ TEX
ISOL_ TI
D
Vssa2
Vcca2
Vss
Vss
Vss
Vss
Tout
LILED#
E
Vssa2
Vcca2
Vss
Vss
Vss
Vss
Vcc
TESTEN
F
RBIAS 100
RBIAS 10
Vss
Vss
Vss
Vss
Vcc
Vcc
G
Vcca
Vssa
TDP
Vcct
Vcct
RDN
Vssr
Vccr
H
Vcca
Vssa
TDN
Vcct
Vcct
RDP
Vssr
Vccr
Figure 6. 82562EP Pinout Diagram
20
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